1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for using latency time between processes for improving wafer-to-wafer uniformity.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and, therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Among the factors that affect semiconductor device manufacturing are wafer-to-wafer variations that are caused by manufacturing problems that include effects of manufacturing tool variations, memory effects of manufacturing chambers, first-wafer effects, and the like. One of the process steps that are adversely affected by such factors is the photolithography overlay process. Overlay is one of several important steps in the photolithography area of semiconductor manufacturing. Overlay control involves measuring the misalignment between two successive patterned layers on the surface of a semiconductor device. Generally, minimization of misalignment errors is important to ensure that the multiple layers of the semiconductor devices are connected and functional. As technology facilitates smaller critical dimensions for semiconductor devices, the need for the reduction of misalignment errors increases dramatically.
Generally, photolithography engineers currently analyze the overlay errors a few times a month. The results from the analysis of the overlay errors are used to make updates to exposure tool settings manually. Some of the problems associated with the current methods include the fact that the exposure tool settings are only updated a few times a month. Furthermore, currently, the exposure tool updates are performed manually.
Generally, a set of processing steps is performed on a lot of wafers on a semiconductor manufacturing tool called an exposure tool or a stepper. The manufacturing tool communicates with a manufacturing framework or a network of processing modules. The manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which the stepper is connected, thereby facilitating communications between the stepper and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. The input parameters that control the manufacturing process are revised periodically in a manual fashion. As the need for higher precision manufacturing processes increases, improved methods are needed to revise input parameters that control manufacturing processes in a more automated and timely manner. Furthermore, wafer-to-wafer manufacturing variations can cause non-uniform quality of semiconductor devices. Latency time between manufacturing processes can cause non-uniform conditions for semiconductor wafers being processed, which can result in non-uniform quality.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for using a latency time period as a control input parameter. A manufacturing run of semiconductor devices is processed. Metrology data from the processed semiconductor devices is acquired. A latency analysis process is performed using the acquired metrology data. A feedback/feed-forward modification process is performed in response to the latency analysis process.
In another aspect of the present invention, an apparatus is provided for using a latency time period as a control input parameter. The apparatus of the present invention comprises: a computer system; a manufacturing model coupled with said computer system, said manufacturing model being capable of generating and modifying at least one control input parameter signal; a machine interface coupled with said manufacturing model, said machine interface being capable of receiving process recipes from said manufacturing model; at least one processing tool capable of processing semiconductor wafers and coupled with said machine interface, said processing tool being capable of receiving at least one control input parameter signal from said machine interface; a metrology tool coupled with said processing tool, said metrology tool being capable of acquiring metrology data; a metrology data processing unit coupled with said metrology tool, said metrology data processing unit being capable of organizing said acquired metrology data; a latency calculator coupled with said metrology tool, said latency calculator being capable of calculating a latency time period between a plurality of semiconductor wafer manufacturing processes based upon said metrology data; and a feedback/feed-forward controller coupled with said latency calculator and said computer system, wherein said feedback/feed-forward controller is capable of generating feedback and feed-forward adjustment data and sending them to said computer system for modification of said control system parameters.